Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.   

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Semi and Custom IP team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.  

 We are looking for a Senior Design for Test (DFT) Engineer to join the team. 

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Qualifications

Required Qualifications:

7+ years of related technical engineering experience

•  OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
•  OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
•  OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4+ years of experience in DFT design 
• 1+ years of experience using Tessent DFT tools 

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:

Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.  

Preferred Qualifications: 

• Experience with static timing tools and timing closure 
• Deep knowledge of digital design 
• Understanding of analog/mixed-signal design 
• Expertise in Python, Perl, or TCL scripting and C programming 
• Good communication skills 
• Debugging skills

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

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Responsibilities

• Collaborate with design architects to engineer DFT solutions.

• Work with design and productization teams to ensure proper for stuck-at and transition fault coverage is achieved. 

• Collaborate with Physical Design (PD) team to ensure proper DFT insertion and timing closure. 

• Perform scan Automatic Test Pattern Generation (ATPG) design rule checking, simulation and coverage analysis. 

• Generate manufacturing test patterns.  

• Perform simulation and verification of DFT patterns. 

• Participate alongside IP and productization teams on silicon bring-up and characterization. 

• Generate IP DFT collateral for System on Chip (SoC) integration. 

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